The Block Diagram Editor is a tool for graphical entry of VHDL, Verilog and EDIF designs. It provides designers with a unique and efficient way to create designs for both vendor independent and technology specific block diagrams. It is more convenient to adopt the schematic entry method when the design is in large part structural. It also allows you to mix different types of descriptions. For example, your design can include pieces in "directly" typed HDL code as well as block diagrams and state diagrams.

Benefits of using the Aldec Schematic editor: The Schematic editor supports both bottom-up and top-down methodologies. Schematic libraries for selected vendors allow you to create technology oriented block diagrams. The Hierarchical property of our editor helps you created multiple pages of the schematics for complex blocks. Block diagram files can be translated to VHDL, Verilog or EDIF netlist.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion