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DAC 2008 - 45th Annual Design Automation Conference
Type: Trade Shows
Dates:
Monday, June 09, 2008 - Thursday, June 12, 2008
Location: Anaheim, CA,
Suite number 1600
The 45th Annual Design Automation Conference is near so be sure to register for our product demonstrations and presentations, showcasing innovative solutions that help build true design leaders. As a 24 year veteran technology leader, Aldec provides “The Best EDA Alternatives". If you are interested in design entry, verification, debugging and emulation then you do not want to miss our DAC 2008 presentations.
Please see the available list of product demonstrations below along with several corporate roadmap presentations that will introduce you to class leading tool sets that handle Verilog®, SystemVerilog, VHDL, SystemC, assertions, code coverage, linting, fast debugging, mixed-language simulation and hardware-assisted verification. Learn how to "Transform your ASIC Prototype into Instant Emulation", get "Clean RTL, Everytime" with our Advanced Verilog® STARC® Linting tools, exploit SystemC 2.2/HDL Co-debugging to your advantage and much more. Register to visit with us at DAC 2008, Today!
Sessions:
DAC 2008 Product Demonstrations
Session
Duration
Actel® Prototyping – Antifuse to Flash
[>>>]
45 min.
Add
Aldec and Zuken Tool Integration – FPGA & PCB
[>>>]
45 min.
Add
Constrained-random verification and debugging
[>>>]
45 min.
Add
DO-254 Compliance Tool Set
[>>>]
45 min.
Add
Hardware Assisted Simulation Acceleration and ASIC emulation
[>>>]
45 min.
Add
HDL-DSP co-simulation with Active-HDL and MATLAB®
[>>>]
45 min.
Add
SFM – regression automation
[>>>]
45 min.
Add
SystemC/HDL Co-debugging - ESL
[>>>]
45 min.
Add
SystemVerilog Testbench and OVM Support
[>>>]
45 min.
Add
Verilog® Lint – STARC Design Rules
[>>>]
45 min.
Add
DAC 2008 Corporate and Product Roadmaps
Session
Duration
Active-HDL Product Roadmap
[>>>]
45 min.
Add
Aldec Roadmap and Company Overview Meeting
[>>>]
45 min.
Add
HES Product Roadmap
[>>>]
45 min.
Add
Partner Meeting
[>>>]
45 min.
Add
Press Meeting
[>>>]
45 min.
Add
Riviera-PRO Product Roadmap
[>>>]
45 min.
Add
Upcoming Events
December 2008
Seminars:
FPGA Design and Verification with Active-HDL Workshop
December 05
Taipei, Taiwan
Trade Shows:
FPGA Summit
December 10 - December 11
San Jose, CA
Seminars:
FPGA Design and Verification with Active-HDL Workshop
December 12
Tainan, Taiwan
Seminars:
SystemVerilog Assertions Language and Methodology Overview Seminar
December 16
Sunnyvale, CA
Webinars:
Design Rule Checking Tools: a Key to Avoiding ASIC Re-spins.
December 17
On-Line
Webinars:
Europe - Design Rule Checking Tools: a Key to Avoiding ASIC Re-spins.
December 17
On-Line
January 2009
Webinars:
Actel & Aldec: Innovative Reprogrammable Prototyping for Actel RTAX Space-Flight FPGA Designs
January 15
On-Line
Webinars:
Europe Actel & Aldec: Innovative Reprogrammable Prototyping for Actel RTAX Space-Flight FPGA Designs
January 15
On-Line