Design Rule Checking
ALINT™ is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog® or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, and clock and reset issues prior to simulation and synthesis. ALINT significantly reduces verification time for complex FPGA and ASIC designs, results in uniform, reusable and reliable code and reduces the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. ALINT includes powerful utilities for rule management, violation analysis, and debugging.
Top Features
- Fast design analysis of complex ASIC/FPGA-SOC designs
- Comprehensive set of rules to check most complex design issues
- Integrated results analysis and debugging environment
- Supports IEEE VHDL, Verilog and mixed-language designs
- Supports Custom Design Rules