Aldec - Webinars - Download

Instructions

Date of presentation: Thursday 9/18/2008, 3:00 PM (Central European Summer Time (CEST))

Presenter: Aldec, Inc. Jaroslaw Kaczynski, Technical Marketing Engineer

Abstract: We will explain how an ASIC design can be setup for emulation at 1 to 5 MHz using Design Verification Manager (DVM) – a part of ALDEC’s HES product line. Aldec developed several revolutionary algorithms of FPGA partitioning and cross-chips synchronization that guarantees your ASIC up and running in FPGAs in just a few hours.

Agenda:

· Cross-FPGA design partitioning with signal multiplexing

· External stimulus synchronization

· Driving the emulation

· Integration with prototyping boards

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What FPGAs interest you?:	Actel Altera Lattice Quicklogic Xilinx
Which HDL's interest you?:	Assertions OVL/PSL/SVA SystemC/C/C++ SystemVerilog Verilog VHDL
Are you interested in any specialty solutions:	Actel RTAX prototyping ASIC design rule checking (LINT) ASIC emulation/prototyping DO-254 compliance Matlab/Simulink co-simulation
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