Aldec - Webinars - Download

Build Information

Platform:All Platforms
Release Date:8/27/2009
Build:Europe - Verification Code Longevity - Learn Expert Techniques
Build Type:RTL Simulation & Verification

Instructions

Date: Thursday, August 27, 2009
Time: 3:00 pm – 4:00 pm CEST
Location: On-Line

Abstract:
It seems that we always have to rewrite verification code that we did on a previous project. Why? What can we do to minimize code changes? In this webinar, international author Mike Mintz shares Expert Techniques, based on OOP (Object Oriented Programming) that he uses to make code last. We’ll take a look at how to write adaptable monitors and checkers. Mike will show how to maximize the probability that your code can be adapted to other projects.

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What FPGAs interest you?:	Actel Altera Lattice Quicklogic Xilinx
Which HDL's interest you?:	Assertions OVL/PSL/SVA SystemC/C/C++ SystemVerilog Verilog VHDL
Are you interested in any specialty solutions:	Actel RTAX prototyping ASIC design rule checking (LINT) ASIC emulation/prototyping DO-254 compliance Matlab/Simulink co-simulation
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