Aldec - Riviera-PRO 2010.06 Configurations (Feature Matrix)

Riviera-PRO 2010.06 Configurations (Feature Matrix)

Features	(LV)	(LVT)	(LVT-SV)
	Riviera-PRO 2010.06
Supported Languages
VHDL IEEE 1076 (1987, 1993, 2002 and 2008)	●	●	●
Verilog® HDL IEEE 1364 (1995, 2001 and 2005)	●	●	●
SystemVerilog IEEE 1800™-2005 (Design)	●	●	●
SystemC™ 2.2 IEEE 1666/OSCI 2.2/TLM 2.0		●	●
SystemVerilog IEEE 1800™-2005 (Assertions)		●	●
SystemVerilog IEEE 1800™ (Verification)			●
Design Entry and Design Management
HDL and Text Editor	●	●	●
Syntax highlighting and Auto-Complete (HDL, PSL and SVA)	●	●	●
Design Manager	●	●	●
Customizable GUI Perspectives	●	●	●
Macro, Tcl/TK, Perl and C++ script support	●	●	●
HDL Debug and Analysis
Interactive Code Execution Tracing	●	●	●
Advanced Breakpoint Management	●	●	●
Accelerated Waveform (ASDB)	●	●	●
Hierarchical References to/from VHDL (Signal Agent)	●	●	●
Post Simulation Debug	●	●	●
Multiple Waveform Windows	●	●	●
Waveform Comparision	●	●	●
Assertions in Waveform and Debugging		●	●
Integrated Source Level C/SystemC Debugger		●	●
Memory Viewer		●	●
Synopsys SmartModels®, SWIFT Interface and LMTV		●	●
SpringSoft® Verdi™ FSDB Interface		●	●
X-Trace		●	●
Advanced Dataflow		●	●
Simulation/Verification
Single or Mixed Language	●	●	●
Verilog Programming Language Interfaces (PLI/VPI)	●	●	●
VHDL Programming Language Interface (VHPI)	●	●	●
SystemVerilog IEEE 1800™ DPI 2.0	●	●	●
Value Change Dump (VCD and Extended VCD) Support	●	●	●
Incremental Compilation	●	●	●
Multi-Threaded Compilation	●	●	●
Separate Elaboration	●	●	●
Simulation Model Protection	●	●	●
32/64-Bit Cross-Compatible Libraries	●	●	●
Verilog 2005 IEEE Encryption	●	●	●
VHDL 2008 IEEE Encryption	●	●	●
Xilinx® SecureIP Support	Option (VHDL Only)¹	●	●
64-Bit Simulation		Linux Only	Linux Only
Verilog RTL & Gate Performance Optimization		●	●
VHDL RTL & VITAL Performance Optimization		●	●
Profiler (Performance Metrics)		●	●
SFM (Server Farm Manager)		Option²	●
Hardware Assisted Verification (Acceleration and Emulation)		Option³	Option³
OVM and UVM Support			●
Coverage Tools
Statement, Branch, Expression, Condition and Toggle Coverage		●	●
Functional Coverage in Assertions/Code Coverage		●	●
Aldec Coverage Database (ACDB) - SystemVerilog Functional Coverage Only		●	●
Coverage Viewer with HTML/TXT Reporting		●	●
Path Coverage (VHDL only)		●	●
Co-simulation
Simulink® Co-simulation		●	●
MATLAB® Co-simulation		●	●
Assertions Bundle
PSL IEEE 1850, SystemVerilog IEEE 1800™, OpenVera Assertions		●	●
Design Rule Checking
ALINT™ with Basic Rule Library	Option⁴	●	●
DO-254 Verilog or VHDL Rule Library	Option⁴	Option⁴	Option⁴
STARC® Verilog or VHDL Rule Library	Option⁴	Option⁴	Option⁴
RMM Verilog and VHDL Rule Library	Option⁴	Option⁴	Option⁴
Licensing
Floating License	●	●	●
Supported Platforms
Windows® 7/Vista/XP/2003 - (32/64-Bit)	●	●	●
Linux x86/x86_64	x86 Only	●	●

Notes:
1 - Option for use with VHDL only; included in Mixed/Verilog configurations
2 - Server Farm Manager is a separate Aldec product
3 - Hardware Assisted Verification is a separate Aldec product - HES
4 - ALINT™ is a separate Aldec product, STARC, DO-254 and RMM packages are sold separately