Feedback on this page

  • Company
  • Products
  • Technologies
  • Events
  • Support
  • Downloads
  • Partners
Innovation Builds Leaders
  • Design Creation
    • Schematic / Block Diagram Editor
    • HDL Text Editor
    • State Machine Editor
    • FPGA Project Management
    • IP Core Generator
    • Code to Graphics
    • Testbench Generation
    • Documentation (HTML/PDF)
  • Verification
    • VHDL Simulation
    • Verilog Simulation
    • SystemC
    • SystemVerilog
    • Assertions (PSL, SVA and OVA)
    • Acceleration/Emulation
    • Prototyping
    • Code Coverage
    • Design Rule Checker (LINT)
  • Specialty Solutions
    • In-Hardware Simulation
    • DO-254 Compliance
    • MATLAB/Simulink Co-Simulation
    • Verification IP
    • HDL Regression Manager
    • NIOS II Co-Verification
    • ARM Co-Verification
    • Actel RTAX Prototyping
Messages
Free Advanced Methodology Seminars
News and Events
Upcoming Event
  • Advanced Workshop on HDL Co-Simulation with MATLAB® for Xilinx® DSP Designs
  • (MAPLD) Military Aerospace Programmable Logic Devices Conference
From Press Room
  • Aldec® Announces HES 2008.07 with SCE-MI 2.0 Co-Emulation Debugging and Dynamic Debugging for ASIC Design Emulation
  • Aldec Delivers Clock Domain Crossing (CDC) Solution
  • Aldec Enhances Entire EDA Suite with Key Verification Methodologies
Contact Us · Disclaimer · Home
© Copyright 2008 Aldec, Inc.